Wafer level probing and/or wafer level chip scale package (WLCSP) testing of a complimentary metal-oxide-semiconductor (CMOS) wafer containing a plurality of integrated circuit (IC) dies typically requires communication between the external test equipment (e.g., tester) and the device under test (e.g., an IC die). A primary aspect of the communication is to download a test program from the tester to each IC die on the wafer and then receive the test results to determine whether the IC die under test is a good die or a bad die.
IC dies are increasingly being fabricated with a build-in self-test (BIST) mechanism or function. A BIST function or mechanism permits an IC die to verify all or a portion of the internal functionality of the IC die. Inclusion of a BIST can reduce reliance upon and/or the complexity of external test equipment, thereby reducing test costs. For example, with the inclusion of the BIST mechanism at each IC die, a test program downloaded from the tester may simply initiate execution of the BIST, receive the test result (e.g., pass/fail) from the BIST, and communicate that result back to the tester.
Thus, with the inclusion of a BIST mechanism, wafer level testing is becoming faster due to a reduction in communication between the tester and the devices under test. However, wafer level testing typically entails a process of die-by-die programming and testing in which a probe of the tester must index or step between each of the IC dies on the wafer. The process of indexing or stepping between each of the IC dies on the wafer to perform die-by-die programming and testing is still undesirably time consuming and costly. Therefore, a need exists in the art of wafer level testing to increase the speed of testing and thereby decrease the costs associated with testing.